With the advent of increasing serial interface bit-rates, the need for the development of high-speed Data Recovery Circuits (DRC) has become more and more prevalent. Very high-frequency phase-locked loops (PLLs), picosecond-jitter specifications, high jitter tolerance DRC specifications, plesiochronous/isochronous interfaces, spread-spectrum clocking, as well as low-voltage signaling environments accommodating shrinking transistor geometries have made DRC design very complex. Evaluation of newly developed DRC architectures and implementations has become more difficult and, in some cases impossible, using some of the presently available Bit-Error-Rate Tester (BERT) Equipment. Data-rate performance limitations, signaling electricals, but more importantly, the limited error-event, and error-recovery diagnostics were found to be inadequate for test, performance analysis, and evaluation of new and existing high-speed serial interface DRCs, especially across the various interface media.
Testing high-speed serial interfaces is difficult, the various circuit components making up the front-end receiver, and its respective data recovery circuits, are prone to various types of intermittent errors. Various elements in the serial interface communications interface, such as transmitter signal PLL-jitter, rise/fall time mismatch, interface media insertion loss and reflections, may cause signal distortions and jitter-events beyond the jitter-tolerance threshold of the Data Recovery Circuits (DRC), resulting in Bit errors. Conversely, other errors may result from physical environmental sources, such as, power-supply events, substrate-noise events, and electromagnetic interference (EMI) events. Bit errors may occur as a single-error, or may occur as a Burst-error event, consisting of a sustained sequence of errors. Thus, existing techniques merely count bit/burst errors and are insufficient for capturing and analyzing characteristics of the error-event in order to quickly validate and test high speed serial interfaces.